Rabbit 3000 Microprocessor User's Manual

5. Pin Assignments and Functions

5.1 LQFP Package

5.1.1 Pinout

Rabbit 3000 (AT56C55-IL1T, IL2T)
128-pin Low-Profile Quad Flat Pack (LQFP)
14 × 14 Body, 0.4 mm pitch

Figure 5-1. Package Outline and Pin Assignments

5.1.2 Mechanical Dimensions and Land Pattern

Figure 5-2 shows the mechanical dimensions of the Rabbit 3000 LQFP package.

Figure 5-2. Mechanical Dimensions Rabbit LQFP Package

Figure 5-3 shows the PC board land pattern for the Rabbit 3000 chip in a 128-pin LQFP package. This land pattern is based on the IPC-SM-782 standard developed by the Surface Mount Land Patterns Committee and specified in Surface Mount Design and Land Pattern Standard, IPC, Northbrook, IL, 1999.

Figure 5-3. PC Board Land Pattern for Rabbit 3000 128-pin LQFP

5.2 Ball Grid Array Package

5.2.1 Pinout

Rabbit 3000 (AT56C55-IZ1T, IZ2T)
128-pin Thin Map Ball Grid Array (TFBGA)
10 × 10 Body, 0.8 mm pitch

Figure 5-4. Ball Grid Array Pinout Looking Through the Top of Package

5.2.2 Mechanical Dimensions and Land Pattern

Table 5-2. Ball and Land Size Dimensions

Nominal Ball Diameter (mm)	Tolerance Variation (mm)	Ball Pitch (mm)	Nominal Land Diameter (mm)	Land Variation (mm)
0.3	0.35-0.25	0.8	0.25	0.25-0.20

The design considerations in Table 5-3 are based on 5 mil design rules and assume a single conductor between solder lands.

Table 5-3. Design Considerations
(all dimensions in mm)

Key	Feature	Recommendation
A	Solder Land Diameter	0.254 (0.010)
B	NSMD Defined Land Diameter	0.406 (0.016)
C	Land to Mask Clearance (min.)	0.050 (0.002)
D	Conductor Width (max.)	0.127 (0.005)
E	Conductor Spacing (typ.)	0.127 (0.005)
F	Via Capture Pad (max.)	0.406 (0.016)
G	Via Drill Size (max.)	0.254 (0.010)

Figure 5-5. BGA Package Outline

5.3 Rabbit Pin Descriptions

Table 5-1 lists all the pins on the device, along with their direction, function, and pin number on the package.

Table 5-1. Rabbit Pin Descriptions 

Pin Group	Pin Name	Direction	Function	Pin Numbers LQFP	Pin Numbers TFBGA
Hardware	CLK	Output	Internal Clock	2	B1
	CLK32K	Input	32 kHz Oscillator In	49	L6
	/RESET	Input	Master Reset	46	M5
	RESOUT	Output	Reset Output	50	M6
	XTALA1	Input	Main Oscillator In--if an external clock is used, this pin should be driven by the external clock; see Technical Note TN235 for more information on external oscillator circuits	113	B7
	XTALA2	Output	Main Oscillator Out	114	A7
CPU Buses	ADDR[19:0]	Output	Address Bus	various
	DATA[7:0]	Bidirectional	Data Bus	10-15, 18-19	D4, E1-E4, F1, F4, G0
Status/Control	/WDTOUT	Output	WDT Time-Out	43	J5
	STATUS	Output	Instruction Fetch First Byte	4	C1
	SMODE[1:0]	Input	Bootstrap Mode Select	44, 45	K5, L5
Memory Chip Selects	/CS0	Output	Memory Chip Select 0	7	D1
	/CS1	Output	Memory Chip Select 1	47	J6
	/CS2	Output	Memory Chip Select 2	3	B2
Memory Output Enables	/OE0	Output	Memory Output Enable 0	5	C2
	/OE1	Output	Memory Output Enable 1	95	C12
Memory Write Enables	/WE0	Output	Memory Write Enable 0	86	F9
	/WE1	Output	Memory Write Enable 1	99	B11
I/O Control	/BUFEN	Output	I/O Buffer Enable	42	M4
	/IORD	Output	I/O Read Enable	41	L4
	/IOWR	Output	I/O Write Enable	40	K4
I/O ports	PA[7:0]	Input / Output	I/O Port A	111-104	D7, A8, B8, C8, D8, A9, B9, C9
I/O ports (continued)	PB[7:0]	Input / Output	I/O Port B	123-116	C4, A5, B5, C5, D5, A6, B6, C6
	PC[7:0]	4 In / 4 Out	I/O Port C	66-71, 74, 75	L11, M11, M12, L12, K12, K11, J10, H12
	PD[7:0]	Input / Output	I/O Port D	52-59	K7, L7, M7, J8, K8, L8, M8, J9
	PE[7:0]	Input / Output	I/O Port E	26-31, 34, 35	H4, J1-J4, K1, L1-L2
	PF[7:0]	Input / Output	I/O Port F	127-124, 103-100	A3, B3, A4, B4, A10, B10, A11, A12
	PG[7:0]	Input / Output	I/O Port G	36-38, 60-63	M1, M2, L3, M3, K9, L9, M9, K10
Power, processor core	VDDCORE		+3.3 V	8, 24, 72, 88	D2, E11, H2, J12
Power Processor I/O Ring	VDDIO		+3.3 V	1, 17, 33, 65, 81, 97, 115	A1, C10, D6, F3, G10, K3, M10
Power Battery Backup	VBAT		+3.3 V or battery	51	J7
Ground Processor Core	VSSCORE		Ground	9, 25, 73, 89	D3, E10, H3, J11
Ground Processor I/O Ring	VSSIO		Ground	16, 32, 48, 64, 80, 96, 112, 128	A2, C7, C11, F2, G11, K2, K6, L10

5.4 Bus Timing

The external bus has essentially the same timing for memory cycles or I/O cycles. A memory cycle begins with the chip select and the address lines. One clock later, the output enable is asserted for a read. The output data and the write enable are asserted for a write.

Figure 5-6. Bus Timing Read and Write

In some cases, the timing shown in Figure 5-6 may be prefixed by a false memory access during the first clock, which is followed by the access sequence shown in Figure 5-6. In this case, the address and often the chip select will change values after one clock and assume the final values for the memory to be actually accessed. Output enable and write enable are always delayed by one clock from the time the final, stable address and chip select are enabled. Normally the false memory access attempts to start another instruction access cycle, which is aborted after one clock when the processor realizes that a read data or write data bus cycle is needed. The user should not attempt a design that uses the chip select or a memory address as a clock or state changing signal without taking this into consideration.

5.5 Description of Pins with Alternate Functions

Table 5-2. Pins With Alternate Functions 

Pin Name	Output Function	Input Function	Input Capture Option
PA[7:0]	SLAVE D[7:0], ID[7:0]	SLAVE D[7:0], ID[7:0]
PB7	SLAVEATTN, IA5
PB6	IA4	/ASCS1.
PB5	IA3	SD1
PB4	IA2	SD0
PB3	IA1	/SRD
PB2	IA0	/SWR
PB1	CLKA	CLKA
PB0	CLKB	CLKB
PC7	n/a	RXA	yes
PC6	TXA	n/a
PC5	n/a	RXB	yes
PC4	TXB	n/a
PC3	n/a	RXC	yes
PC2	TXC	n/a
PC1	n/a	RXD	yes
PC0	TXD	n/a
PD7	APWM3*	ARXA	yes
PD6	ATXA
PD5	APWM2*	ARXB	yes
PD4	ATXB
PD3			yes
PD2
PD1			yes
PD0
PE7	I7	/SCS (slave chip select)
PE6	I6
PE5	I5	INT1B
PE4	I4	INT0B
PE3	I3
PE2	I2
PE1	I1	INT1A
PE0	I0	INT0A
PF7	PWM3	AQD2A	yes
PF6	PWM2	AQD2B
PF5	PWM1	AQD1A	yes
PF4	PWM0	AQD1B
PF3		QD2A	yes
PF2		QD2B
PF1	CLKC	QD1A, CLKC	yes
PF0	CLKD	QD1B, CLKD
PG7	APWM1*	RXE	yes
PG6	TXE
PG5	RCLKE	RCLKE, ARXE*	yes
PG4	TCLKE	TCLKE, ARCLKE*
PG3	APWM0*	RXF
PG2	TXF
PG1	RCLKF	RCLKF, ARXF*
PG0	TCLKF	TCLKF, ARCLKF*

* Introduced with Rabbit 3000A chip

The alternate output functions identified in Table 5-2 are configured by setting the appropriate bits in the Paralle Port x Function Register.

Table 5-3. Parallel Port x Alternate Functions

Parallel Port x Function Register (PCFR) (Address = 0x0055) (PDFR) (Address = 0x0065) (PEFR) (Address = 0x0075) (PFFR) (Address = 0x003D) (PGFR) (Address = 0x004D)
Bit(s)	Value	Description
7:0	0	The corresponding port bit functions normally.
	1	The corresponding port bit carries its alternate signal as an output. See Table 5-4 below. Only the bits that have alternate functions listed in Table 5-4 actually have a control bit in these registers. That is, there are four in Port C, four in Port D, eight in Port E, four in Port F, and eight in Port G.

Table 5-4. Parallel Port x Alternate Functions Control Bits

Alternate Output Function
Bit	Port B	Port C	Port D	Port E	Port F	Port G
7	/SLAVEATTN, IA5		APWM3	I7	PWM3	APWM1
6	IA4	TXA	ATXA	I6	PWM2	TXE
5	IA3		APWM2	I5	PWM1	RCLKE
4	IA2	TXB	ATXB	I4	PWM0	TCLKE
3	IA1			I3		APWM0
2	IA0	TXC		I2		TXF
1	CLKA			I1	CLKC	RCLKF
0	CLKB	TXD		I0	CLKD	TCLKF

5.6 DC Characteristics

Table 5-5. Rabbit 3000 Absolute Maximum Ratings

Symbol	Parameter	Maximum Rating
TA	Operating Temperature	-55° to +85°C
TS	Storage Temperature	-65° to +150°C
	Maximum Input Voltage: Oscillator Buffer Input 5-V-tolerant I/O	VDD + 0.5 V 5.5 V
VDD	Maximum Operating Voltage	3.6 V

Stresses beyond those listed in Table 5-5 may cause permanent damage. The ratings are stress ratings only, and functional operation of the Rabbit 3000 chip at these or any other conditions beyond those indicated in this section is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect the reliability of the Rabbit 3000 chip.

Table 5-6 outlines the DC characteristics for the Rabbit 3000 at 3.3 V over the recommended operating temperature range from T_A = -55°C to +85°C, V_DD = 3.0 V to 3.6 V.

Table 5-6. 3.3 Volt DC Characteristics

Symbol	Parameter	Test Conditions	Min	Typ	Max	Units
VDD	Supply Voltage		3.0	3.3	3.6	V
VIH	High-Level Input Voltage		2.0			V
VIL	Low-Level Input Voltage				0.8	V
VOH	High-Level Output Voltage	IOH = 6.8 mA, VDD = VDD (min)	0.7 × VDD			V
VOL	Low-Level Output Voltage	IOL = 6.8 mA, VDD = VDD (min)			0.4	V
IIH	High-Level Input Current (absolute worst case, all buffers)	VIN = VDD, VDD = VDD (max)			10	µA
IIL	Low-Level Input Current (absolute worst case, all buffers)	VIN = VSS, VDD = VDD (max)	-10			µA
IOZ	High-Impedance State Output Current (absolute worst case, all buffers)	VIN = VDD or VSS, VDD = VDD (max), no pull-up	-10		10	µA

5.7 I/O Buffer Sourcing and Sinking Limit

Unless otherwise specified, the Rabbit I/O buffers are capable of sourcing and sinking 6.8 mA of current per pin at full AC switching speeds. The limits are related to the maximum sustained current permitted by the metallization on the die.