User's Manual
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| Rabbit 3000 Microprocessor User's Manual |
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7. Miscellaneous Functions
7.1 Processor Identification
Four read-only registers are provided to allow software to identify the Rabbit microprocessor and recognize the features and capabilities of the chip. Five bits in each of these registers are unique to each version of the chip. One register is reserved for the on-chip flash memory configuration (GROM), one register is reserved for the on-chip RAM memory configuration (GRAM), one register identifies the CPU (GCPU), and the final register is reserved for revision identification (GREV). The Rabbit 3000 does not contain on-chip SRAM or flash memories.
7.2 Rabbit Oscillators and Clocks
The Rabbit 3000 usually requires two separate clocks. The main clock normally drives the processor core and most of the peripheral devices, and the 32.768 kHz clock drives the battery-backable time-date clock and other circuitry.
An oscillator buffer is built into the Rabbit 3000 that may be used to implement the main processor oscillator (Figure 7-1). For lowest power an external oscillator may be substituted for the built-in oscillator circuit. An oscillator implemented using the built in buffer accepts crystals up to a frequency of 27 MHz (first overtone crystals only). This frequency may be then doubled by the clock doubler. The component values shown in the figure for the oscillator circuits are subject to adjustment depending on the crystal used and the operating frequency.
The Rabbit 3000 has a spectrum spreader unit that modifies the clock by shortening and lengthening clock cycles. The effect of this is to spread the spectral energy of the clock harmonics over a fairly wide range of frequencies. This limits the peak energy of the harmonics and reduces EMI that may interfere with other devices as well as reducing the readings in government mandated EMI tests. The spectrum spreader has two operating modes, normal spreading and strong spreading. The spreader can also be turned off.
The 32.768 kHz clock is primarily used to clock the on-chip real-time clock. In addition, it is also used to support remote cold boot via Serial Port A, driving the 2400 baud communications used to initiate the cold boot. Another function of the 32.768 kHz oscillator is to drive the low power sleepy mode with the main oscillator shut down to reduce power. The 32.768 kHz clock can be left out of a system provided that its functions are not required.
TN235, External 32.768 kHz Oscillator Circuits, provides further information on oscillator circuits and selecting the values of components to use in the oscillator circuit.
Table 7-6. Clock Select Field of GCSR
7.3 Clock Doubler
The clock doubler is provided to allow a lower frequency crystal to be used for the main oscillator and to provide an added range of clock frequency adjustability. The clock doubler is controlled via the Global Clock Double Register as shown in Table 7-7.
The clock doubler uses an on-chip delay circuit that must be programmed by the user at startup if there is a need to double the clock. Table 7-8 lists the recommended delays for the Global Clock Double Register for various oscillator frequencies.
Table 7-8. Recommended Delays Set In GCDR for Clock Doubler
When the clock doubler is used and there is no subsequent division of the clock, the output clock will be asymmetric, as shown in Figure 7-2.
The doubled-clock low time is subject to wide (50%) variation since it depends on process parameters, temperature, and voltage. The times given above are for a supply voltage of 3.3 V and a temperature of 25°C. The doubled-clock low time increases by 20% when the voltage is reduced to 2.5 V, and increases by about 40% when the voltage is reduced further to 2.0 V. The values increase or decrease by 1% for each 5°C increase or decrease in temperature. The doubled clock is created by xor'ing the delayed and inverted clock with itself. If the original clock does not have a 50-50 duty cycle, then alternate clocks will have a slightly different length. Since the duty cycle of the built-in oscillator can be as asymmetric as 52-48, the clock generated by the clock doubler will exhibit up to a 4% variation in period on alternate clocks. This does not affect the no-wait states memory access time since two adjacent clocks are always used. However, the maximum allowed clock speed must be slightly reduced if the clock is supplied via the clock doubler. The only signals clocked on the falling edge of the clock are the memory and I/O write pulses and the early option memory output enable. See Chapter 8 for more information on the early output enable and write enable options.
The spectrum spreader either stretches or shrinks the low plateau of the clock by a maximum of 3 ns for the normal spreading and 4.5 ns for the strong spreading. If the clock doubler is used this will cause an additional asymmetry between alternate clock cycles.
The power consumption is proportional to the clock frequency, and for this reason power can be reduced by slowing the clock when less computing activity is taking place. The clock doubler provides a convenient method of temporarily speeding up or slowing down the clock as part of a power management scheme.
7.4 Clock Spectrum Spreader
When enabled the spectrum spreader stretches and compresses the clocks in a complex pattern that results in spreading the energy in the clock harmonics over a wide range of frequencies. The spectrum spreader has a normal and a strong setting. With either setting the peak spectral strength of the clock harmonics is reduced by approximately 15 dB for frequencies above 100 MHz. For lower frequencies the strong spreading has a greater effect in reducing the peak spectral strength as shown in the figure below.
In the normal spectrum spreading mode, the maximum shortening of the clock cycle is 3 nanoseconds at 3.3 V and 25°C. In the strong spreading mode the maximum shortening of a clock cycle under the same conditions is 4.5 ns. The reduction in peak spectral strength is roughly independent of the clock frequency. Special precautions must be followed in setting the GCM0R and GCM1R registers (see Section 15.2, "Using the Clock Spectrum Spreader").
7.5 Chip Select Options for Low Power
Some types of flash memory and RAM consume power whenever the chip select is enabled even if no signals are changing. The chip select behavior of the Rabbit 3000 can be modified to reduce unnecessary power consumption when the Rabbit 3000 is running at a reduced clock speed. The short chip select option can be enabled when the processor clock is divided (by 4, 6, or 8) so as to run at a lower speed.
The short chip select option is exercised with clock select bits 4:2 of the GCSR register as shown in Table 7-6. Whether the chip select is normal or short is then determined by whether bit 4 in the GPSCR register is 0 or 1.
When the short chip select option is enabled, the chip select delays turning on until the end of the of the memory cycle when it turns on for the last 2 undivided clocks. If the clock is divided by 6, the memory read cycle with no wait states would normally be 12 undivided clocks long. With the short chip select, the chip select is on for only 2/12 clocks for a memory duty cycle of 1/6. If wait states are added, the duty cycle is reduced even more. For example, if there is one wait state and the clock is divided by 6, the memory bus cycle will be 18 undivided clocks long and the duty cycle will be 2/18 = 1/9 with the short chip select option enabled.
When the short chip select option is enabled, the interrupt sequence will attempt to write the return address to the stack if an interrupt takes place immediately after an internal or an external I/O instruction. The chip select will be suppressed during the write cycle, and the correct return address will not be stored on the stack. This happens only when an interrupt takes place immediately after an I/O instruction when the short chip select option is enabled. Therefore, when using the short chip select option, ensure that interrupts are disabled during I/O instructions (or do not use short chip select). Interrupts can be disabled for a single I/O instruction as shown in the following example.
PUSH IP ; save interrupt state
IPSET 3 ; interrupts off
IOE LD a,(hl) ; typical I/O instruction
POP IP ; reenable interruptsWhen the 32.768 kHz clock is used as the main processor clock (sleepy mode) the memory duty cycle can be reduced by enabling a self-timed chip select mode. When the 32.768 kHz clock is used, the clock period is approximately 32 µs, and a normal memory read cycle without wait states will be approximately 64 µs. No more than a few hundred nanoseconds are needed to read the memory. The main oscillator is normally shut down when operating at 32 kHz, and no faster clock is available to time out a short chip select cycle. To provide for a low-memory-duty cycle, a chip select and memory read can take place under control of a delay timer that is on the chip. The cycle starts at the start of the final 64 µs clock of the memory cycle and can be set to enable chip select for a period in the range of 70 to 200 ns. The data are clocked in early at the end of the delay-driven cycle. The chip select duty cycle is very small, about 0.2/128 = 1/600.
When operating in the 32 kHz mode, it is also possible to further divide the clock to a frequency as low as 2 kHz, further reducing execution speed and current consumption.
It is anticipated that these measures would reduce operating current consumption to as low as 20 µA plus some additional leakage that would be significant at high operating temperatures.
7.6 Output Pins CLK, STATUS, /WDTOUT, /BUFEN
Certain output pins can have alternate assignments as specified in Table 7-9.
7.7 Time/Date Clock (Real-Time Clock)
The time/date clock (RTC) is a 48-bit (ripple) counter that is driven by the 32.768 kHz oscillator. The RTC is a modified ripple counter composed of six separate 8-bit counters. The carries are fed into all six 8-bit counters at the same time and then ripple for 8 bits. The time for this ripple to take place is a few nanoseconds per bit, and certainly should not should not exceed 200 ns for all 8 bits, even when operating at low voltage.
The 48 bits are enough to count up 272 years at the 32 kHz clock frequency. By convention, 12 AM on January 1, 1980, is taken as time zero. Rabbit Semiconductor software ignores the highest order bit, giving the counter a capacity of 136 years from January 1, 1980. To read the counter value, the value is first transferred to a 6-byte holding register. Then the individual bytes may be read from the holding registers. To perform the transfer, any data bits are written to RTC0R, the first holding register. The counter may then be read as six 8-bit bytes at RTC0R through RTC5R. The counter and the 32 kHz oscillator are powered from a separate power pin that can be provided with power while the remainder of the chip is powered down. This design makes battery backup possible. Since the processor operates on a different clock than the RTC, there is the possibility of performing a transfer to the holding registers while a carry is taking place, resulting in incorrect information. In order to prevent this, the processor should do the clock read twice and make sure that the value is the same in both reads.
If the processor is itself operating at 32 kHz, the read-clock procedure must be modified since a number of clock counts would take place in the time needed by the slow-clocked processor to read the clock. An appropriate modification would be to ignore the lower bytes and only read the upper 5 bytes, which are counted once every 256 clocks or every 1/128th of a second. If the read cannot be performed in this time, further low-order bits can be ignored.
The RTC registers cannot be set by a write operation, but they can be cleared and counted individually, or by subset. In this manner, any register or the entire 48-bit counter can be set to any value with no more than 256 steps. If the 32 kHz crystal is not installed and the input pin is grounded, no counting will take place and the six registers can be used as a small battery-backed memory. Normally this would not be very productive since the circuitry needed to provide the power switchover could also be used to battery-back a regular low-power static RAM.
7.8 Watchdog Timer
The watchdog timer is a 17-bit counter. In normal operation it is driven by the 32.768 kHz clock. When the watchdog timer reaches any of several values corresponding to a delay of from 0.25 to 2 seconds, it "times out." When it times out, it emits a 1-clock pulse from the watchdog output pin and it resets the processor via an internal circuit. To prevent this timeout, the program must "hit" the watchdog timer before it times out. The hit is accomplished by storing a code in WDTCR. Note that although a watchdog timeout resets the processor, it does not reset the timeout period stored in the WDTCR. This was done intentionally because an application may require the initialization of the processor resulting from the watchdog timeout to be based on a specific timeout period that is different from that of the reset initialization.
The watchdog timer may be disabled by storing a special code in the WDTTR register. Normally this should not be done unless an external watchdog device is used. The purpose of the watchdog is to unhang the processor from an endless loop caused by a software crash or a hardware upset.
It is important to use extreme care in writing software to hit the watchdog timer (or to turn off the watchdog timer). The programmer should not sprinkle instructions to hit the watchdog timer throughout his program because such instructions can become part of an endless loop if the program crashes and thus disable the recovery ability given by having a watchdog.
The following is a suggested method for hitting the watchdog. An array of up to 10 bytes is set up in RAM. Each of these bytes is a virtual watchdog. To hit a virtual watchdog, a number is stored in a byte. Every virtual watchdog is counted down by an interrupt routine driven by a periodic interrupt. This can happen every 62.5 ms. If none of the virtual watchdogs has counted down to zero, the interrupt routine hits the hardware watchdog. If any have counted down to zero, the interrupt routine disables interrupts, and then enters an endless loop waiting for the reset. Hits of the virtual watchdogs are placed in the user's program at "must exercise" locations. The Dynamic C User's Manual provides further information on the use of virtual watchdogs.
The code to do this may also hit the watchdog with a 0.25-second period to speed up the reset. Such watchdog code must be written so that it is highly unlikely that a crash will incorporate the code and continue to hit the watchdog in an endless loop. The following suggestions will help.
- Place a jump to self before the entry point of the watchdog hitting routines. This prevents entry other than by a direct call or jump to the routine.
- Before calling the routine, set a data byte to a special value and then check it in the routine to make sure the call came from the right caller. If not, go into an endless loop with interrupts disabled.
- Maintain data corruption flags and/or checksums. If these go wrong, go into an endless loop with interrupts off.
7.9 System Reset
The Rabbit 3000 contains a master reset input (pin 46), which initializes everything in the device except for the Real-Time Clock (RTC). This reset is delayed until the completion of any write cycles in progress to prevent potential corruption of memory. If no write cycles are in progress the reset takes effect immediately. The reset sequence requires a minimum of 128 cycles of the fast oscillator to complete, even if no write cycles were in progress at the start of the reset. Reset forces both the processor clock and the peripheral clock in the divide-by-eight mode. Note that if the processor is being clocked from the 32 kHz clock, the 128 cycles of the fast oscillator will probably not be sufficient to allow any writes in progress to be completed before the reset sequence completes and the clocks switch to divide-by-eight mode.
During reset /CS1 is high impedance and all of the other memory and I/O control signals are held inactive (High). After the /RESET signal becomes inactive (High) the processor begins fetching instructions and the memory control signals begin normal operation. Note that the default values in the Memory Bank Control Registers select four wait states per access, so the initial program fetch memory reads are 48 clock cycles long (8 x (2 + 4)). Software can immediately adjust the processor timing to whatever the system requires.
/CS1 is high-impedance during reset (and during power-down, when only VBAT is powered) to allow an external RAM connected to /CS1 to be powered by VBAT. This is possible because the /CS1 pin is powered by VBAT. In this case an external pull-up resistor (to VBAT) is required on /CS1 to keep the RAM deselected during power-down. If the external RAM connected to /CS1 is not powered by VBAT, so that any information held within it is lost during power-down, no pull-up resistor on /CS1 is appropriate, as this would add leakage (through the protection diode) to drain VBAT. The RESOUT signal, which is High during reset and power-down, can be used to control an external power switch to disconnect VDD from supplying VBAT.
The default selection for the memory control signals consists of /CS0 and /OE0, and writes are disabled. This selection can also be immediately programmed to match the hardware configuration. A typical sequence would be to speed up the clock to full speed, followed by selection of the appropriate number of wait states and the chip select signals, output enable signals and write enable signals. At this point software would usually check the system status to determine what type of reset just occurred and begin normal operation.
The default values for all of the peripheral control registers are shown with the following register listing. The registers within the CPU affected by reset are the Stack Pointer (SP), the Program Counter (PC), the IIR register, the EIR register, and the IP register. The IP register is set to all ones (disabling all interrupts), while all of the other listed CPU registers are reset to all zeros.
Table 7-14 describes the state of the I/O pins after an external reset is recognized by the Rabbit CPU. Note that the /RESET signal must be held low for three clocks for the processor to begin the reset sequence. There is no facility to tri-state output lines such as the address lines and the memory and I/O control lines.
* A low is recognized internally by the processor after a reset
* The default state of the I/O ports after the completion of the reset and initialization sequences
7.10 Rabbit Interrupt Structure
An interrupt causes a call to be executed, pushing the PC on the stack and starting to execute code at the interrupt vector address. The interrupt vector addresses have a fixed lower byte value for all interrupts. The upper byte is adjustable by setting the registers EIR and IIR for external and internal interrupts respectively. There are only two external interrupts generated by transitions on certain pins in Parallel Port E.
The interrupt vectors are shown in Table 6-2.
The interrupts differ from most Z80 or Z180 interrupts in that the 256-byte tables pointed to EIR and IIR contain the actual instructions beginning the interrupt routines rather than a 16-bit pointer to the routine. The interrupt vectors are spaced 16 bytes apart so that the entire code will fit in the table for very small interrupt routines.
Interrupts have priority 1, 2 or 3. The processor operates at priority 0, 1, 2 or 3. If an interrupt is being requested, and its priority is higher than the priority of the processor, the interrupt will take place after then next instruction. The interrupt automatically raises the processor's priority to its own priority. The old processor priority is pushed into the 4-position stack of priorities contained in the IP register. Multiple devices can be requesting interrupts at the same time. In each case there is a latch set in the device that requests the interrupt. If that latch is cleared before the interrupt is latched by the central interrupt logic, then the interrupt request is lost and no interrupt takes place. This is shown in Table 7-15. The priorities shown in this table apply only for interrupts of the same priority level and are only meaningful if two interrupts are requested at the same time. Most of the devices can be programmed to interrupt at priority level 1, 2 or 3.
In the case of the external interrupts the only action that will clear the interrupt request is for the interrupt to take place, which automatically clears the request. A special action must be taken in the interrupt service routine for the other interrupts.
7.10.1 External Interrupts
There are two external interrupts. Each interrupt has two input pins that can be used to trigger the interrupt. The inputs have a pulse catcher that can detect rising, falling, or both edges. The pulse needs to be present for a least three peripheral clocks to be detected.
The external interrupts take place on a transition of the input, which is programmable for rising, falling, or both edges. Each of the interrupt pins has its own catcher device that can be programmed separately to catch the edge transition and request the interrupt.
When the interrupt takes place, both pulse catchers associated with that interrupt are automatically reset. If both edges are detected before the corresponding interrupt takes place, because the triggering edges occur nearly simultaneously or because the interrupts are inhibited by the processor priority, then there will be only one interrupt for the two edges detected. The interrupt service routine can read the interrupt pins via Parallel Port E and determine which lines experienced a transition, provided that the transitions are not too fast. Interrupts can also be generated by setting up the matching port E bit as an output and toggling the bit.
External interrupts are cleared automatically during the processor Interrupt Acknowledge cycle. The Interrupt Acknowledge cycle will always immediately follow an Instruction Fetch 1 cycle. This instruction byte is ignored, and will be the first byte fetched upon returning from the interrupt. Interrupt Acknowledge cycles are always followed by two memory writes to push the contents of the PC onto the stack. Execution then begins at the appropriate interrupt vector location.
7.10.2 Interrupt Vectors: INT0 - EIR,0x00/INT1 - EIR,0x08
When it is desired to expand the number of interrupts for additional peripheral devices, the user should use the interrupt routine to dispatch interrupts to other virtual interrupt routines. Each additional interrupting device will have to signal the processor that it is requesting an interrupt. A separate signal line is needed for each device so that the processor can determine which devices are requesting an interrupt.
The following code shows how the interrupt service routines can be written.
; External interrupt Routine #0 (programmed priority could be 3)
int2:
PUSH IP ; save interrupt priority
IPSET 1 ; set to priority really desired (1, 2, etc.)
; insert body of interrupt routine here
;
OPP IP ; get back entry priority
IPRES ; restore interrupted routine's priority
RET ; return from interrupt7.11 Bootstrap Operation
The device provides the option of bootstrap from any of three sources: from the Slave Port, from Serial Port A in clocked serial mode, or from Serial Port A in asynchronous mode. This is controlled by the state of the SMODE pins after reset. Bootstrap operation is disabled if (SMODE1, SMODE0) = (0, 0).
Bootstrap operation inhibits the normal fetch of code from memory, and instead substitutes the output of a small internal boot ROM for program fetches. This bootstrap program reads groups of three bytes from the selected peripheral device. The first byte is the most significant byte of a 16-bit address, followed by the least-significant byte of a 16-bit address, followed by a byte of data. The bootstrap program then writes the byte of data to the downloaded address and jumps back to the start of the bootstrap program. The most significant bit of the address is used to determine the destination for the byte of data. If this bit is zero, the byte is written to the memory location addressed by the downloaded address. If this bit is one, the byte is written to the internal peripheral addressed by the downloaded address. Note that all of the memory control signals continue to operate normally during bootstrap.
Execution of the bootstrap program automatically waits for data to become available from the selected peripheral, and each byte transferred automatically resets the watchdog timer. However, the watchdog timer still operates, and bytes must be transferred often enough to prevent the watchdog timer from timing out.
Bootstrap operation is terminated when the SMODE pins are set to zero. The SMODE pins are sampled just prior to fetching the first instruction of the bootstrap program. If the SMODE pins are zero, instructions are fetched from normal memory starting at address 0x0000. The Slave Port Control register allows the bootstrap operation to be terminated remotely. Writing a one to bit 7 of this register causes the bootstrap operation to terminate immediately. So the sequence 0x80, 0x24, and 0x80 will terminate bootstrap operation.
Bootstrap operation is not restricted to the time immediately after reset because the boot ROM is addressed by only the four least significant bits of the address. So any time that the address ends in four zeros, if the SMODE pins are non-zero and bit 7 of the SPCR is zero, the bootstrap program will begin execution. This allows in-line downloading from the selected bootstrap port. Upon completion of the bootstrap operation, either by returning the SMODE pins to zero or setting the bit in the SPCR, execution will continue from where it was interrupted for the bootstrap operation.
The Slave Port is selected for bootstrap operation when (SMODE1, SMODE0) = (0, 1). In this case the pins of Parallel Port A are used for a byte-wide data bus, and selected pins of Parallel Ports B and E are used for the Slave Port control signals. Only Slave Port Data Register 0 is used for bootstrap operation, and any writes to the other data registers will be ignored by the processor, and can actually interfere with the bootstrap operation by masking the Write Empty signal.
Serial Port A is selected for bootstrap operation as a clocked serial port when SMODE = 10. In this case bit 7 of Parallel Port C is used for the serial data and bit 1 of Parallel Port B is used for the serial clo
