Table of Contents
- 1.1 Features and Specifications Rabbit 3000
- 1.2 Summary of Rabbit 3000 Advantages
- 1.3 Differences Rabbit 3000 vs. Rabbit 2000
- 2.1 The Rabbit 8-bit Processor vs. Other Processors
- 2.2 Overview of On-Chip Peripherals and Features
- 2.2.1 5 V Tolerant Inputs
- 2.2.2 Serial Ports
- 2.2.3 System Clock
- 2.2.4 32.768 kHz Oscillator Input
- 2.2.5 Parallel I/O
- 2.2.6 Slave Port
- 2.2.7 Auxiliary I/O Bus
- 2.2.8 Timers
- 2.2.9 Input Capture Channels
- 2.2.10 Quadrature Decoder Inputs
- 2.2.11 Pulse Width Modulation Outputs
- 2.2.12 Spread Spectrum Clock
- 2.2.13 Separate Core and I/O Power Pins
- 2.3 Design Standards
- 2.3.1 Programming Port
- 2.3.2 Standard BIOS
- 2.4 Dynamic C Support for the Rabbit
- 3.1 Processor Registers
- 3.2 Memory Mapping
- 3.2.1 Extended Code Space
- 3.2.2 Separate I and D Space - Extending Data Memory
- 3.2.3 Using the Stack Segment for Data Storage
- 3.2.4 Practical Memory Considerations
- 3.3 Instruction Set Outline
- 3.3.1 Load Immediate Data to a Register
- 3.3.2 Load or Store Data from or to a Constant Address
- 3.3.3 Load or Store Data Using an Index Register
- 3.3.4 Register-to-Register Move
- 3.3.5 Register Exchanges
- 3.3.6 Push and Pop Instructions
- 3.3.7 16-bit Arithmetic and Logical Ops
- 3.3.8 Input/Output Instructions
- 3.4 How to Do It in Assembly Language--Tips and Tricks
- 3.4.1 Zero HL in 4 Clocks
- 3.4.2 Exchanges Not Directly Implemented
- 3.4.3 Manipulation of Boolean Variables
- 3.4.4 Comparisons of Integers
- 3.4.5 Atomic Moves from Memory to I/O Space
- 3.5 Interrupt Structure
- 3.5.1 Interrupt Priority
- 3.5.2 Multiple External Interrupting Devices
- 3.5.3 Privileged Instructions, Critical Sections and Semaphores
- 3.5.4 Critical Sections
- 3.5.5 Semaphores Using Bit B,(HL)
- 3.5.6 Computed Long Calls and Jumps
- 4.1 Precisely Timed Output Pulses
- 4.1.1 Pulse Width Modulation to Reduce Relay Power
- 4.2 Open-Drain Outputs Used for Key Scan
- 4.3 Cold Boot
- 4.4 The Slave Port
- 4.4.1 Slave Rabbit As A Protocol UART
- 5.1 LQFP Package
- 5.1.1 Pinout
- 5.1.2 Mechanical Dimensions and Land Pattern
- 5.2 Ball Grid Array Package
- 5.2.1 Pinout
- 5.2.2 Mechanical Dimensions and Land Pattern
- 5.3 Rabbit Pin Descriptions
- 5.4 Bus Timing
- 5.5 Description of Pins with Alternate Functions
- 5.6 DC Characteristics
- 5.7 I/O Buffer Sourcing and Sinking Limit
- 6.1 Default Values for all the Peripheral Control Registers
- 7.1 Processor Identification
- 7.2 Rabbit Oscillators and Clocks
- 7.3 Clock Doubler
- 7.4 Clock Spectrum Spreader
- 7.5 Chip Select Options for Low Power
- 7.6 Output Pins CLK, STATUS, /WDTOUT, /BUFEN
- 7.7 Time/Date Clock (Real-Time Clock)
- 7.8 Watchdog Timer
- 7.9 System Reset
- 7.10 Rabbit Interrupt Structure
- 7.10.1 External Interrupts
- 7.10.2 Interrupt Vectors: INT0 - EIR,0x00/INT1 - EIR,0x08
- 7.11 Bootstrap Operation
- 7.12 Pulse Width Modulator
- 7.13 Input Capture
- 7.14 Quadrature Decoder
- 8.1 Interface for Static Memory Chips
- 8.2 Memory Mapping Overview
- 8.3 Memory-Mapping Unit
- 8.4 Memory Interface Unit
- 8.5 Memory Bank Control Registers
- 8.5.1 Optional A16, A19 Inversions by Segment (/CS1 Enable)
- 8.6 Allocation of Extended Code and Data
- 8.7 Instruction and Data Space Support
- 8.8 How the Compiler Compiles to Memory
- 9.1 Parallel Port A
- 9.2 Parallel Port B
- 9.3 Parallel Port C
- 9.4 Parallel Port D
- 9.5 Parallel Port E
- 9.6 Parallel Port F
- 9.6.1 Using Parallel Port A and Parallel Port F
- 9.7 Parallel Port G
- 11.1 Timer A
- 11.1.1 Timer A I/O Registers
- 11.1.2 Practical Use of Timer A
- 11.2 Timer B
- 11.2.1 Using Timer B
- 12.1 Serial Port Register Layout
- 12.2 Serial Port Registers
- 12.3 Serial Port Interrupt
- 12.4 Transmit Serial Data Timing
- 12.5 Receive Serial Data Timing
- 12.6 Clocked Serial Ports
- 12.7 Clocked Serial Timing
- 12.7.1 Clocked Serial Timing With Internal Clock
- 12.7.2 Clocked Serial Timing with External Clock
- 12.8 Synchronous Communications on Ports E and F
- 12.9 Serial Port Software Suggestions
- 12.9.1 Controlling an RS-485 Driver and Receiver
- 12.9.2 Transmitting Dummy Characters
- 12.9.3 Transmitting and Detecting a Break
- 12.9.4 Using A Serial Port to Generate a Periodic Interrupt
- 12.9.5 Extra Stop Bits, Sending Parity, 9th Bit Communication Schemes
- 12.9.6 Parity, Extra Stop Bits with 7-Data-Bit Characters
- 12.9.7 Parity, Extra Stop Bits with 8-Data-Bit Characters
- 12.9.8 Supporting 9th Bit Communication Protocols
- 12.9.9 Rabbit-Only Master/Slave Protocol
- 12.9.10 Data Framing/Modbus
- 13.1 Hardware Design of Slave Port Interconnection
- 13.2 Slave Port Registers
- 13.3 Applications and Communications Protocols for Slaves
- 13.3.1 Slave Applications
- 13.3.2 Master-Slave Messaging Protocol
- 14.1 Low-Power Design
- 15.1 Power Supply Connections and Board Layout
- 15.2 Using the Clock Spectrum Spreader
- 16.1 Memory Access Time
- 16.2 I/O Access Time
- 16.3 Further Discussion of Bus and Clock Timing
- 16.4 Maximum Clock Speeds
- 16.5 Power and Current Consumption
- 16.6 Current Consumption Mechanisms
- 16.7 Sleepy Mode Current Consumption
- 16.8 Memory Current Consumption
- 16.9 Battery-Backed Clock Current Consumption
- 16.10 Reduced-Power External Main Oscillator
- 17.1 The BIOS
- 17.1.1 BIOS Services
- 17.1.2 BIOS Assumptions
- 17.2 Virtual Driver
- 17.2.1 Periodic Interrupt
- 17.2.2 Watchdog Timer Support
- 18.1 Power Management Support
- 18.2 Reading and Writing I/O Registers
- 18.2.1 Using Assembly Language
- 18.2.2 Using Library Functions
- 18.3 Shadow Registers
- 18.3.1 Updating Shadow Registers
- 18.3.2 Interrupt While Updating Registers
- 18.3.3 Write-only Registers Without Shadow Registers
- 18.4 Timer and Clock Usage
- 19.1 Load Immediate Data
- 19.2 Load & Store to Immediate Address
- 19.3 8-bit Indexed Load and Store
- 19.4 16-bit Indexed Loads and Stores
- 19.5 16-bit Load and Store 20-bit Address
- 19.6 Register to Register Moves
- 19.7 Exchange Instructions
- 19.8 Stack Manipulation Instructions
- 19.9 16-bit Arithmetic and Logical Ops
- 19.10 8-bit Arithmetic and Logical Ops
- 19.11 8-bit Bit Set, Reset and Test
- 19.12 8-bit Increment and Decrement
- 19.13 8-bit Fast A Register Operations
- 19.14 8-bit Shifts and Rotates
- 19.15 Instruction Prefixes
- 19.16 Block Move Instructions
- 19.17 Control Instructions - Jumps and Calls
- 19.18 Miscellaneous Instructions
- 19.19 Privileged Instructions
- A.1 Use of the Programming Port as a Diagnostic/Setup Port
- A.2 Alternate Programming Port
- A.3 Suggested Rabbit Crystal Frequencies
- B.1 Discussion of Fixes and Improvements
- B.1.1 Rabbit Internal I/O Registers
- B.1.2 Peripheral and ISR Address
- B.1.3 Revision-Level ID Register
- B.1.4 System/User Mode
- B.1.5 Memory Protection
- B.1.6 Stack Protection
- B.1.7 RAM Segment Relocation
- B.1.8 Secondary Watchdog Timer
- B.1.9 New Opcodes
- B.1.10 Expanded I/O Memory Addressing
- B.1.11 External I/O Improvements
- B.1.12 Short Chip Select Timing for Writes
- B.1.13 Pulse Width Modulator Improvements
- B.1.14 Quadrature Decoder Improvements
- B.2 Pins with Alternate Functions
- C.1 System/User Mode Opcodes
- C.2 System/User Mode Registers
- C.3 Interrupts
- C.3.1 Peripheral Interrupt Prioritization
- C.4 Using the System/User Mode
- C.4.1 Memory Protection Only
- C.4.2 Mixed System/User Mode Operation
- C.4.3 Complete Operating System