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3. Design Implementation and Information

This chapter discusses the implementation of the RabbitFLEX™ SBC features. We start with information about the basic bare board, which is used as the foundation for all RabbitFLEX™ SBC boards. This foundation board is called the base board. Next, we discuss the physical and logical components that make up the feature set selected during the online ordering process.

3.1 General Board Information

This section describes the RabbitFLEX BL300F base board and provides a high-level diagram of the subsystem options.

3.1.1 Base Board Layout

The base board for a RabbitFLEX BL300F is pictured in Figure 3.1.

Figure 3.1 Base Board for RabbitFLEX BL300F

3.1.2 Board-Specific Information

The PowerCore module and the board to which it is attached are linked by more than their physical connection. Switching the mated core module is not recommended, as the calibration and design numbers are contained in the core module and will thus no longer match the board.

3.1.2.1 System ID Block

The System ID block is a reserved area in flash memory that contains identification information for the core module and the design number for the RabbitFLEX BL300F. All RabbitFLEX BL300F devices have System ID blocks of version 5 or later. The information fields contained in the System ID block are described in the Rabbit 3000 Designer's Handbook.

3.1.2.2 User Block

The System ID block has information about the User block. The User block is where calibration constants are stored. There is memory in the User block for other persistent data that may be required by your application.

3.2 Cells and Circuits

The magic of a flex board is the innovative design of the cells, which are abstracted to a level that allows them to implement one of multiple functions that may be chosen by you, the board designer.

3.2.1 Cell Definition

Cells can be configured or unconfigured. Unconfigured cells are the basic structure unit at the PCB level. An unconfigured cell can be configured to implement one of several logical functions, thus making it a configured cell. A configured cell is one in which circuitry has been assembled to form a single function on a RabbitFLEX board, such as an I/O pin or a serial port.

3.2.2 Cell Descriptions

There are different types of cells available. Each one is designed to handle different types of circuits. Each I/O pin is supported by a one-transistor or two-transistor cell on the RabbitFLEX BL300F board.

The one- and two-transistor cell layouts pictured in Figure 3.2 and Figure 3.3 can be used along with the board layout pictured in Figure 3.4 to determine the placement of components on your board. The pad labels (R2A, R2B, Q1B, etc.) that you see in the cell layout diagrams correspond to the component designators in the circuit schematics.

For example if you look at the circuit diagram for the 1.4 V trigger threshold digital input, you will see that the 100 ohm resistor is labeled "R6." Looking at the one-transistor cell layout, "R6" is located in the lower-right corner of the cell. The physical placement of "R6" is different when a two-transistor cell is used to implement the 1.4 V digital input.

3.2.2.1 One-Transistor Cells

Figure 3.2 shows the complete layout of a one-transistor cell. A one-transistor cell can handle digital inputs, certain outputs, bidirectional logic and keypads. The one-transistor cells on connector J4 can also be used as analog inputs.

Figure 3.2 One-Transistor Cell

3.2.2.2 Two-Transistor Cells

A two-transistor cell is required for all sourcing outputs and the 1 A sinking output. The two-transistor cells on connector J3 can also be used as analog inputs. You can use any circuit that can be placed in a one-transistor cell, but not vice-versa.

Figure 3.3 Two-Transistor Cell

3.2.3 Board Map

The board map shown in Figure 3.4 identifies the cell placement for each of the I/O pins. Each rectangle labeled "Jx PIN y" starts as an unconfigured cell before a circuit is selected and placed on it, causing it to become a configured cell.

Figure 3.4 Map of Cells Supporting I/O Pins on Connectors J1-J5

Digital I/O is routed to a digital interface cell, which is routed to the core module. Analog inputs are routed to an analog input interface cell, which is also routed to the core module. An analog input cell takes in the ramp generator output, the eight possible analog inputs and three selector pins. A background process continually reads the analog inputs and stores the last values read.

Figure 3.5 shows the locations of the digital and analog interface cells corresponding to connectors J1-J5.

Figure 3.5 Map of Digital and Analog Input Interface Cells