1. The Rabbit RIO


Rabbit RIO User's Manual

1. The Rabbit RIO

1.1 Overview

The Rabbit RIO is a peripheral device designed to be incorporated into systems requiring versatile timing controls and a broader range of functionality. The Rabbit RIO can be used with any microprocessor.

The Rabbit RIO communicates with the microprocessor in either a parallel or a serial mode. The particular communication mode is determined during power-up. In the parallel mode, the chip communicates with the microprocessor through a parallel bus with eight data bits, five address bits, and four control bits. The serial mode can be used for bidirectional data flow on one wire or via the SPI and RabbitNet protocols. In the serial mode, the parallel data lines are available to be used as general-purpose I/O. The multiple communication modes allow the Rabbit RIO to be a part of a wide variety of systems that use any one of these communication methods.

Implementing the Rabbit RIO as a RabbitNet hub provides a simple, efficient, and flexible means of establishing a network of RabbitNet peripheral cards. The RabbitNet architecture allows a hub to connect to seven peripheral cards, and support for two levels of hubs allows a master device to control up to 49 RabbitNet peripheral cards.

The design of the Rabbit RIO's I/O blocks allows any of the eight identical I/O blocks, each with four bits or I/O pins, to be programmed to perform any number of different functions, including a pulse-width modulator, a pulse-position modulator, event counters, quadrature decoders, pulse measurements, and I/O, including pin-pair protection for applications such as H-bridge drivers.

The main clock can be used directly by each I/O block, or it may be prescaled down to a lower frequency. Either clock source can be used by the 16-bit counter, which is the core of each I/O block. This counter is complemented by a number of registers that provide access and control to the counter for the various Rabbit RIO functions that it involves.

The Rabbit RIO can be incorporated without any glue logic in a Rabbit-based system, enabling a more efficient use of resources. Rabbit's Dynamic C software allows for seamless integration of hardware and software. Dynamic C provides a complete set of function calls to enable you to use the Rabbit RIO without having to write any additional drivers.

The Rabbit RIO can operate at clock speeds up to 40 MHz. It is powered by 3.3 V, but the I/O are 5 V tolerant. The Rabbit RIO is packaged in a 64-pin 10 mm × 10mm TQFP, making its small footprint and low profile ideal for embedded applications.

1.2 Key Features

5 V tolerant

Clock speed up to 40 MHz

64-pin 10 mm × 10 mm TQFP package

Multiple communication interfaces — SPI, parallel, and RabbitNet

8 independent functional I/O blocks with 4 pins each

Any pin on each I/O block is capable of:

u Generating PWM outputs and variable-phase PWM outputs
u Pulse count
u Input capture (pulse length or frequency)
u Decoding quadrature signals
u Provide extended I/O pins to the microprocessor
u Pin-pair protection for driving H bridges

Up to 32 digital I/O lines, up to 4 general-purpose inputs

Global or block synch input to coordinate outputs

Interrupt request pin

RoHS compliant

High-performance 8-bit device requires no glue logic to Rabbit systems

RabbitNet hub feature allows control of up to seven RabbitNet devices in each of two levels for a total of up to 49 RabbitNet devices

Functionality well-suited for machine control

Dynamic C libraries allow for Rabbit RIO to be up and running in no time

Small footprint and multiple functions allow for versatile system

1.3 Development and Evaluation Tools

Rabbit also has an application kit featuring the Rabbit RIO to provide the harware and software tools to help you use the Rabbit RIO for I/O expansion.

RIO Programmable I/O Kit [Part No. 101-1147 (North American markets) and Part No. 101-1148 (overseas markets)]—comes with two CD-ROMs that includes Dynamic C 10.11 or a later version, an RCM4110 RabbitCore module, and a RIO Prototyping Board. The software bundle on the supplemental CD provides the Dynamic C function calls and sample programs that illustrate the use of the Rabbit RIO chip included on the RIO Prototyping Board and can serve as a template for you to develop your own application.

1.4 Block Diagram of Rabbit RIO I/O Blocks

1.5 Pin Functions and Descriptions

Pin Group

Pin Name

Direction

Function

Hardware
/RESET
Input
Master Reset

CLK
Input
Clock In

CPU Buses
BLOCK[2:1] or GPIN[2:1]
BLOCK[0]
G//B
/P/I
Input
Address Bus or GPI1.

D7/SERCLK
D6/SERI
D5/BL6Pin[3]
D4/BL6Pin[2]
D3/BL6Pin[1]
D2/BL7Pin[3]
D1/BL7Pin[2]
D0/BL7Pin[1]
Bidirectional
Parallel Data Bus or
Serial Control Bus &
I/O Block Pins

Status & Control
/CS
Input
I/O Chip Select

/IORD or GPIN[4]
Input
I/O Read Enable or GPI^*

/IOWR or GPIN[3]
Input
I/O Write Enable or GPI^*

/INT
Output
Interrupt Request

/WAIT/SERO
Output
Wait Request or
Serial Out

SER//PAR
Input
Serial/Parallel Bus Select

Shared
GSYNC
Input
Global Sync

I/O Pins
BL0Pin[3:0] –
BL5Pin[3:0] &
BL6Pin[0] &
BL7Pin[0]
Input/Output
I/O Block Pins

Power
VDDINT
VDDIO
Power
Internal Power
I/O Power

Ground
VSSINT
VSSIO
Ground
Internal Ground
I/O Ground

^* The GPI options are general-purpose inputs when operating in a serial mode.

1.6 Pinouts

Figure 1-1. Parallel Pinout

Figure 1-2. Serial Pinout — SPI Interface Mode

Figure 1-3. Serial Pinout — RabbitNet Device Interface Mode

Figure 1-4. Serial Pinout — RabbitNet Hub Interface Mode

Figure 1-5. General Pinout

1.7 Mechanical Dimensions and Land Pattern — TQFP Package

Figure 1-6. Mechanical Dimensions Rabbit RIO TQFP Package

Figure 1-7 shows the PC board land pattern for the Rabbit RIO in a 64-pin TQFP package. This land pattern is based on the IPC-SM-782 standard developed by the Surface Mount Land Patterns Committee and specified in Surface Mount Design and Land Pattern Standard, IPC, Northbrook, IL, 1999.

Figure 1-7. PC Board Land Pattern for Rabbit RIO 64-pin TQFP

1.8 DC Characteristics

Table 1-1. Preliminary DC Electrical Characteristics

Parameter

Symbol

Min

Typ

Max

Operating Temperature

TA

-40°C

85°C

Storage Temperature

-55°C

125°C

Core

Core Supply Voltage

VDDCORE

3.0 V

3.3 V

3.6 V

Core Current @ 22.1184 MHz, 25°C

ICORE

31.3 mA

Core current @ 11.0592 MHz, 25°C

16.3 mA

Core current @ 7.3728 MHz, 25°C

11.0 mA

Core current @ 3.6864 MHz, 25°C

5.5 mA

I/O Ring

I/O Ring Supply Voltage

VDDIO

3.0 V

3.3 V

5.0 V

I/O Ring Current @ 22.1184 MHz, 25°C

IIO

1.1 mA

I/O Ring Current @ 11.0592 MHz, 25°C

IIO

1.0 mA

I/O Ring Current @ 7.3728 MHz, 25°C

0.9 mA

I/O Ring Current @ 3.6864 MHz, 25°C

0.9 mA

Input Low Voltage (VDDIO = 3.3 V)

VIL

0.8 V

Input High Voltage (VDDIO = 3.3 V)

VIH

2.0 V

Output Low Voltage (VDDIO = 3.3 V)

VOL

0.4 V

Output High Voltage (VDDIO = 3.3 V)

VOH

2.4 V

Output Drive

IDRIVE

8 mA

1.9 AC Characteristics

Table 1-2. Preliminary AC Electrical Characteristics

Parameter

Symbol

Min

Typ

Max

Clock Frequency

f_main

40 MHz

1.10 Memory Access Times

All access time measurements are taken at 50% of the signal height.

1.10.1 Parallel Mode

Table 1-3. Parallel Bus Read Time Delays
(VDD = 3.3 V ± 10%, TA = -40°C to 85°C)

Parameter

Symbol

Min

Typ

Max

Clock to Address Delay

T_adr

6 ns

Clock to Chip Select Delay

T_IOCS

6 ns

Clock to Output Enable Delay

T_IORD

6 ns

Data Setup Time

T_setup

1 ns

Data Hold Time

T_hold

0 ns

Table 1-4. Parallel Bus Write Time Delays
(VDD = 3.3 V ± 10%, TA = -40°C to 85°C)

Parameter

Symbol

Min

Typ

Max

Clock to Address Delay

T_adr

6 ns

Clock to Chip Select Delay

T_IOCS

6 ns

Clock to Write Strobe Delay

T_IOWR

6 ns

High Z to Data Valid Relative to Clock

T_DHZV

10 ns

Data Valid to High Z Relative to Clock

T_DVHZ

10 ns

Figure 1-8. Memory Read and Write Cycles

1.10.2 SPI/RabbitNet Mode

Table 1-5. SPI/RabbitNet Bus Access Time Delays
(VDD = 3.3 V ± 10%, TA = -40°C to 85°C)

Parameter

Symbol

Min

Typ

Max

Serial Clock Period

T_CP

25 ns

Serial Clock Pulse Width High

T_CH

12 ns

Serial Clock Pulse Width Low

T_CL

12 ns

Chip Select Fall to Input Data Valid

T_CSD

0 ns

Chip Select Leading Time Before First Clock Edge

T_L

25 ns

Chip Select Trailing Timer After Last Clode Edge

T_T

25 ns

Input Data Setup Time

T_DS

12 ns

Input/Output Data Hold Time

T_DH

12 ns

Chip Select Pulse High

T_CSW

100 ns

Figure 1-9. SPI/RabbitNet Bus Access Time Delays

Pin Group	Pin Name	Direction	Function
Hardware	/RESET	Input	Master Reset
	CLK	Input	Clock In
CPU Buses	BLOCK[2:1] or GPIN[2:1] BLOCK[0] G//B /P/I	Input	Address Bus or GPI1.
	D7/SERCLK D6/SERI D5/BL6Pin[3] D4/BL6Pin[2] D3/BL6Pin[1] D2/BL7Pin[3] D1/BL7Pin[2] D0/BL7Pin[1]	Bidirectional	Parallel Data Bus or Serial Control Bus & I/O Block Pins
Status & Control	/CS	Input	I/O Chip Select
	/IORD or GPIN[4]	Input	I/O Read Enable or GPI^*
	/IOWR or GPIN[3]	Input	I/O Write Enable or GPI^*
	/INT	Output	Interrupt Request
	/WAIT/SERO	Output	Wait Request or Serial Out
	SER//PAR	Input	Serial/Parallel Bus Select
Shared	GSYNC	Input	Global Sync
I/O Pins	BL0Pin[3:0] – BL5Pin[3:0] & BL6Pin[0] & BL7Pin[0]	Input/Output	I/O Block Pins
Power	VDDINT VDDIO	Power	Internal Power I/O Power
Ground	VSSINT VSSIO	Ground	Internal Ground I/O Ground

***Table 1-1. Preliminary DC Electrical Characteristics***
Parameter	Symbol	Min	Typ	Max
Operating Temperature	TA	-40°C		85°C
Storage Temperature	-55°C		125°C
Core	Core Supply Voltage	VDDCORE	3.0 V	3.3 V	3.6 V
Core Current @ 22.1184 MHz, 25°C	ICORE		31.3 mA
Core current @ 11.0592 MHz, 25°C		16.3 mA
Core current @ 7.3728 MHz, 25°C		11.0 mA
Core current @ 3.6864 MHz, 25°C		5.5 mA
I/O Ring	I/O Ring Supply Voltage	VDDIO	3.0 V	3.3 V	5.0 V
I/O Ring Current @ 22.1184 MHz, 25°C	IIO		1.1 mA
I/O Ring Current @ 11.0592 MHz, 25°C	IIO		1.0 mA
I/O Ring Current @ 7.3728 MHz, 25°C		0.9 mA
I/O Ring Current @ 3.6864 MHz, 25°C		0.9 mA
Input Low Voltage (VDDIO = 3.3 V)	VIL		0.8 V
Input High Voltage (VDDIO = 3.3 V)	VIH		2.0 V
Output Low Voltage (VDDIO = 3.3 V)	VOL		0.4 V
Output High Voltage (VDDIO = 3.3 V)	VOH		2.4 V
Output Drive	IDRIVE			8 mA

***Table 1-2. Preliminary AC Electrical Characteristics***
Parameter	Symbol	Min	Typ	Max
Clock Frequency	f_main			40 MHz

Table 1-3. Parallel Bus Read Time Delays
(VDD = 3.3 V ± 10%, TA = -40°C to 85°C)
Parameter	Symbol	Min	Max
Clock to Address Delay	T_adr		6 ns
Clock to Chip Select Delay	T_IOCS		6 ns
Clock to Output Enable Delay	T_IORD		6 ns
Data Setup Time	T_setup	1 ns
Data Hold Time	T_hold	0 ns

Table 1-4. Parallel Bus Write Time Delays
(VDD = 3.3 V ± 10%, TA = -40°C to 85°C)
Parameter	Symbol	Max
Clock to Address Delay	T_adr	6 ns
Clock to Chip Select Delay	T_IOCS	6 ns
Clock to Write Strobe Delay	T_IOWR	6 ns
High Z to Data Valid Relative to Clock	T_DHZV	10 ns
Data Valid to High Z Relative to Clock	T_DVHZ	10 ns

Table 1-5. SPI/RabbitNet Bus Access Time Delays
(VDD = 3.3 V ± 10%, TA = -40°C to 85°C)
Parameter	Symbol	Min
Serial Clock Period	T_CP	25 ns
Serial Clock Pulse Width High	T_CH	12 ns
Serial Clock Pulse Width Low	T_CL	12 ns
Chip Select Fall to Input Data Valid	T_CSD	0 ns
Chip Select Leading Time Before First Clock Edge	T_L	25 ns
Chip Select Trailing Timer After Last Clode Edge	T_T	25 ns
Input Data Setup Time	T_DS	12 ns
Input/Output Data Hold Time	T_DH	12 ns
Chip Select Pulse High	T_CSW	100 ns

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