User's Manual
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| Rabbit RIO User's Manual |
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2. Master-Level Features
2.1 Overview
The Rabbit RIO uses master-level registers to access individual I/O blocks or to control their overall function. Unlike block registers, master registers can be accessed directly through the five-bit address and eight-bit data bus. In the parallel communication mode, these two buses are accessed through address and data bus pins. In the serial communication mode, the data and address must be decoded from the serial bit stream. Changing the communication mode is a simple matter of pulling the G//B, /P/I, BLOCK[0], and SER//PAR pins high or low.
2.2 Block Diagram
2.3 Clocks
Even though the Rabbit RIO has just one Master Clock pin, the timing of each I/O block is still versatile because the Master Precaler will allow any 8-bit prescale of the master clock to be used by the I/O blocks. Once the prescale value is set in the Master Prescale Register (MPR), any I/O block can be set to use either the precaled clock or the master clock directly. Resetting bit 3 of the I/O block's Mode Register (MR) allows the I/O block to use the master clock; setting bit 3 allows the I/O block to use the prescaler.
2.4 Reset
A reset signal can be triggered from multiple sources. A hardware reset is generated by pulling the reset pin low. This will cause all the master and block-level registers to go back to their original startup state. Section 3.2 lists the reset states for each register. Another method of resetting all the registers is through a software reset, which can be accomplished by setting bit 7 of the Master Control Register (MCR). Note that pin-pair protection can only be disabled through a hardware reset.
Additional hardware and software reset options are available at the block level. Such a reset will simply reset the counter for that I/O block, as opposed to resetting the whole chip. The synch signal is used to perform these resets, and there are multiple sources for the synch signal that are specified by the I/O block's Synch Control Register (SCR). This register will specify whether the global synch pin or which one of the four I/O block pins will provide the synch signal.
2.5 Bus Interface
The Rabbit RIO is designed to be connected to the processor data bus, the processor I/O bus, a clocked serial interface, or a RabbitNet master without any glue logic. Unless the Rabbit RIO is acting as a RabbitNet hub, it has all the same functionality regardless of the communication mode — it simply communicates differently in the various communication modes.
When using the parallel communication mode, not all the I/O blocks have complete I/O capability. With this interface, Blocks 6 and 7 each have only one pin available for I/O.
The serial mode is enabled by tying the SER//PAR input high. The six possibilities for the serial interface are shown in Table 2-1.
With a clocked serial interface, data are transferred to and from the Rabbit RIO in address and data cycles. First, the byte of address information is shifted into the chip, and then the byte of data is either shifted in or out of the chip. The active low chip select must remain active for the duration of each byte transfer, but is allowed to go inactive between transfers. The read/write bit is shifted with the address to signal the Rabbit RIO what kind of transfer is requested and sets the direction. Transfers can be either LSB-first or MSB-first. When using the clocked serial interface, all eight I/O blocks have full I/O capabilities.
As a RabbitNet device, the Rabbit RIO implements the RabbitNet specification, including the watchdog function. All RabbitNet transfers are either read-only or are simultaneous read and write (fully duplex). Data are always transferred MSB-first in this mode. When using the Rabbit RIO as a RabbitNet device, all eight I/O blocks have full I/O capabilities.
As a RabbitNet hub, the Rabbit RIO implements the RabbitNet specification for a hub and can be used as either a first- or second-level hub. Only one I/O block has I/O capability, as the pins that are normally used for the other seven I/O blocks are connected to downstream RabbitNet devices.
2.5.1 Parallel Mode
The parallel mode is selected by tying the SER//PAR input low. This mode is completely asynchronous. This makes the chip useful in systems that do not use Rabbit microprocessors.
The address bus consists of a three-bit I/O block address (BLOCK[2:0]) to select the appropriate I/O block, a Pointer/Indirect (/P/I) bit to select between the two externally addressable registers in each I/O block, and the Global/Block (G//B) bit to select between a global access and a block access.
All external transactions are synchronized internally to the clock, which requires a recovery time of four clock cycles between external accesses. In other words, the maximum rate at which external accesses can occur is once every four internal clock cycles. The /WAIT signal is activated until the Rabbit RIO is ready to accept or supply data during a transaction. The /WAIT signal enforces the recovery time between external transactions, and in the case of a read, is guaranteed to be deasserted once the read data are valid.
A read transaction is shown below. The data bus is driven while /IORD and /CS are both active. The address on the address bus must remain valid for the duration of the transaction, but there is no hold time relative to the trailing edge of /IORD or /CS.
A write transaction is shown below. The data bus is latched at the end of the transaction, with no hold time. As in the case of a read, the address on the address bus must remain valid for the duration of the transaction.
Table 2-2 lists the suggested connections to the Rabbit RIO for the parallel mode using the auxiliary I/O bus.
* Rabbit RIO /CS may be connected to PE1 or any other available pin on Parallel Port E, or it may be pulled low.
2.5.2 Serial Mode — Clocked Serial Interface
The clocked serial interface, which includes the two-wire data option (SPI) and the one-wire data option (bidirectional data), is selected by tying both the SER//PAR and G//B inputs high. The two-wire data option (SERIAL IN and SERIAL OUT) is selected by tying the /P/I pin low. The LSB-first serial data option is selected with BLOCK[0] low, and the MSB-first serial data option is selected with BLOCK[0] high. The direction of serial transfer is selected with a bit in the address byte, which must be shifted into the chip as the first phase of a data transfer cycle. The /CS signal will still function as the chip select for this communication mode.
The two-wire data option (SPI) is a half duplex interface where data from the microprocessor travel to the Rabbit RIO on one line, and data from the Rabbit RIO travel to the microprocessor on another line, but not at the same time. A synchronous clock is shared between the two devices, but only the microprocessor drives that signal.
The single-wire data option works similarly to the two-wire data option, except that data are transferred between devices through one line. In this case, a transfer starts with a write operation to the Rabbit RIO to indicate whether this will be a write or a read cycle and to or from which register. In this operation, the master, typically the microprocessor, will drive the data and clock lines. If the cycle happens to be a read cycle, the address write operation will be followed by a read operation. The clock will continue to be driven by the master, but the data will be driven by the Rabbit RIO. On the other hand, if the cycle happens to be a write cycle, then the address write operation will be followed by a write operation. The clock and the data will continue to be driven by the master.
A serial mode address transfer is shown below. The five address bits function identically to the corresponding address signals in the parallel processor interface. The R//W bit controls the direction of the data transfer (high for read, low for write). Note that the value on the SERI signal is sampled by the rising edge of the SERCLK signal.
A serial mode write transfer is shown below. Note that the recovery time restriction still applies in the serial bus cases, but now there is no mechanism to enforce this restriction since the /WAIT signal has become the serial output (SERO) signal. The wait time should not be an issue as long as SERCLK frequency is not more than CLK/4.
A serial mode read transfer is shown below for the case of separate serial input and output signals.
The same read transfer is shown below when using a bidirectional serial data signal. Note that any external driver on the serial data signal must be tristated before the falling edge of the serial clock. The serial data signal is driven by the device only until shortly after the rising edge of the serial clock to prevent possible bus contention.
Table 2-3 lists the suggested connections to the Rabbit RIO for the SPI clocked serial interface where data flow unidirectionally on two lines (two-wire data flow).
Table 2-4 lists the suggested connections to the Rabbit RIO for the clocked serial interface where data flow bidirectionally on one line (one-wire data flow).
2.5.3 Serial Mode — RabbitNet Device Interface
The RabbitNet device interface option is selected by tying the SER//PAR pin high and the G//B and /P/I pins low. The table below shows the RabbitNet addressing. Additional information on RabbitNet and the RabbitNet peripheral cards is available in the RabbitNet Peripheral Card User's Manual.
In order to take advantage of the SPI-like interface, the Rabbit RIO will always write back the status or echo the SERO stream, which the master can check to verify the data integrity. All data bits are transmitted and received MSB first, however, the order of bytes is little endian for RabbitNet devices transferring multiple bytes.
The protocol for communicating to the Rabbit RIO is somewhat different with RabbitNet than other forms of serial communication. To communicate with the Rabbit RIO directly from a master, a command byte must be sent out first. This byte tells the Rabbit RIO the type of transaction being initiated, determined by the two most significant bits, and which register to access, determined by the six least significant bits. At the same time the command byte is being transmitted to the Rabbit RIO, the status byte is transmitted from the Rabbit RIO. Since the status byte is transmitted automatically, its register does not have a register address. A read or a write cycle will begin immediately after the command cycle. If reading, the master will continue to drive the clock, but will be getting data driven by the Rabbit RIO. If writing, the master will drive both the clock and the data going into the Rabbit RIO.
Table 2-6 lists the suggested connections to the Rabbit RIO for the RabbitNet device interface via Serial Port C. Serial Port B or Serial Port D may also be used.
Table 2-6. Rabbit RIO Connections
— RabbitNet Device Serial InterfacePulled up
Pulled down
Pulled down
Serial input to Rabbit RIO
Serial output from Rabbit RIO
Clock input to Rabbit RIO
2.5.4 Serial Mode — RabbitNet Hub Interface
The RabbitNet hub interface option is selected by tying the SER//PAR and /P/I pins high and tying the G//B pin low. The table below shows the RabbitNet hub addressing.
As a RabbitNet hub, the Rabbit RIO essentially becomes a different device. A hub is responsible for switching its upstream port to one of its downstream ports. The Rabbit RIO is no longer the target device, but becomes a device that reroutes signals to the appropriate RabbitNet device on its ports. A maximum of two levels of hubs are allowed in any RabbitNet network. Each hub can multiplex at most seven downstream ports.
When the master initializes the network, it must first broadcast commands to its RabbitNet port to assign each hub as a first level hub or a second level hub. It will then proceed to enumerate all devices attached to the available hubs and list them in a tabled set in memory. In this way, all devices can be easily tracked and accessed.
Table 2-8 lists the suggested connections to the Rabbit RIO for the RabbitNet hub interface via Serial Port C. Serial Port B or Serial Port D may also be used.
Table 2-8. Rabbit RIO Connections
— RabbitNet Hub Serial InterfacePulled up
Pulled down
Pulled up
Serial input to Rabbit RIO
Serial output from Rabbit RIO
Clock input to Rabbit RIO
Chapter 9 provides additional information on using the Rabbit RIO as a RabbitNet hub.
2.6 Synchronization
The Rabbit RIO is non-specific to any system, meaning it will work no matter what system it is incorporated into. If the Rabbit RIO is used in a Rabbit-based system, then special logic can be used to synchronize its timing. Bit 1 of the Master Control Register can be reset to disable synchronizing logic when using a non-Rabbit-based system, or set to enable the special synchronization logic when used in a Rabbit-based system.
The synchronous bus timing option can be used when the Rabbit RIO is connected to a Rabbit microprocessor, and the RIO clock is supplied by the CLK output of the Rabbit microprocessor. The option reduces the access recovery time when the Rabbit RIO is communicating directly with a Rabbit microprocessor so that back-to-back reads and writes can be supported. Much of the synchronization logic in the Rabbit RIO can be bypassed in this case because the phase relationships for the address, data, and control signals are already known. The bit is ignored in the serial communication modes and the RabbitNet mode.
2.7 Interrupts
Interrupts can be enabled on the Rabbit RIO as an alternative to polling to provide a more efficient use of processor time. Master-level registers provide a means for interrupt control, but the exact nature of the interrupt is determined by block-level interrupt registers. To enable interrupts, Bit 0 of the Master Control Register must be set. When an I/O block triggers an interrupt, the Rabbit RIO will pull /INT low. Upon receiving the interrupt, the master can read the Master Status Register from the Rabbit RIO to determine which I/O block(s) invoked the interrupt, service the interrupt, and clear that particular interrupt in the block's Status Register.
2.8 Registers
The external address bus selects the registers according to Table 2-9 below. Each I/O block is accessed indirectly through just two external I/O addresses.
The addressing in the RabbitNet mode is similar, except the RabbitNet addresses are six bits wide, with many of the lowest address reserved for commands and configuration. In this case, the Rabbit RIO addresses are relocated to the upper 32 bytes of the RabbitNet address space, that is, the most significant bit of the RabbitNet address is set to one to access these Rabbit RIO registers (see Table 2-7).
2.9 Register Descriptions
A number of external addresses are used for registers that provide global control and status for the Rabbit RIO. Master-level registers are accessed directly through the address bus, and block-level registers are accessed indirectly through the pointer registers.
2.9.1 Master Control Register
The Master Control Register has three functions:
When the Rabbit RIO is interfaced with a Rabbit microprocessor, faster operation is possible by enabling synchronous bus timing via bit 1. This option can be used when the Rabbit RIO is connected to a Rabbit microprocessor, and the RIO clock is supplied by the CLK output of the Rabbit microprocessor.
2.9.2 Master Status Register
The Master Status Register allows a processor to determine which I/O block signaled an interrupt.
2.9.3 Master Prescale Register
Each of the eight I/O blocks has the option of either using the master clock directly or using a scaled version of that clock determined by the Master Prescale Register. The prescale value will apply universally to all the I/O blocks.
2.9.4 Master Alternate Data Register
In the serial mode, certain pins that were used in the parallel mode for bus control are available as general-purpose input-only pins. The Master Alternate Data Register will allow the processor to read the state of these pins.
Bits 7, 4, 1, and 0 are used to establish the type of serial communication interface, and their pins are not generally used as general-purpose inputs. These pins are used to set the communication mode, and their use should not be changed since that would affect the chip's behavior.
2.9.5 Master Protection Command Register
Pin-pair protection is enabled by writing to the Master Protection Command Register to protect the upper two bits or the lower two bits of any I/O block. The "safe" state is considered to be the state of the protected pins at the time this register is written to; therefore, an "unsafe" state is the bitwise complement of that output. The other two possible bit combinations are considered "active" states since they are allowable outputs.
For example, let's say that "11" is the disallowed state (but "00", "01", and "10" are allowed). To enable pin-pair protection on two pins of an I/O block, set the output on both pins to 0 (the "safe" state, which is the complement of the disallowed state) and write the appropriate value to MPCR to enable pin-pair protection. Once this value is written, the protection will be enabled for the selected pair of pins, resulting in the following outputs.
NOTE When pin-pair protection is enabled, the pins will be forced to the safe state between each output transition for a period determined by the Master Protection Prescale Register. 2.9.6 Master Protection Prescale Register
The value written to this register determines the dead-time time constant, a number between 0 and 255. The dead time is useful in preventing overlap during pin-output transitions. When pin-pair protection is enabled on a pair of pins, the Rabbit RIO forces the pins into a "safe" state during the dead time between signal transitions on those pins.
The main Rabbit RIO clock will be divided by (n + 1) to give the dead-time time constant. The actual dead-time will vary between (n + 1) and (2*n + 2) Rabbit RIO clocks.
For example, let's say that "11" is the disallowed state ("00" is then the "safe" state, and "01" and "10" are allowed). When pin-pair protection is enabled for a pair of pins, to switch from "01" to "10", the output will first switch from "01" to "00" for the dead-time specified in MPPR, and then to "10".
2.9.7 Watchdog Timer Registers
All RabbitNet devices and hubs implement a watchdog timer. This timer is restarted on receipt of any command from the master. If it times out, then the device assumes that the communication link has been lost, and the device places itself in a fail-safe state. Once in the fail-safe state, the device must ignore any commands that would cause its output state to change until a soft reset is triggered through the RabbitNet Reset Status Register. This watchdog register is enable only when the Rabbit RIO is being used in the RabbitNet communication mode.
2.9.8 Pointer Registers
Each I/O block has a Pointer Register that will allow access to the block's internal registers. The lower five bits of this register holds the pointer (or address) to the internal registers. The most significant bit allows auto-incrementing of this pointer for fast configuration.
2.9.9 Indirect Registers
The Indirect Register of each I/O block allows reads and/or writes to the address pointed to by the Pointer Register.
