3. Block-Level Features
3.1 Overview
The Rabbit RIO has eight identical I/O blocks. Although these I/O blocks can operate in a number of different modes, the core of each I/O block is a 16-bit counter that can be clocked by the master clock for the device, by the 8-bit Master Prescaler, or by an external source. This counter is accompanied by a number of registers that are updated with control register values each time the counter rolls over. This buffering allows the control register to be updated during the current count cycle with values to be used during the next count cycle. The registers that are buffered this way are the 16-bit reload register and the four 16-bit match registers. The four 16-bit match registers each generate an output pulse when the count is equal to the value programmed into that register. These pulses can be used to set or reset any of the outputs from the I/O block. The 16-bit limit register determines when the counter will be reloaded. Some of the different operating modes that are possible are described in more detail in the later chapters.
3.1.1 Simplified Block Diagram
3.2 Internal Block Registers
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Pointer Register
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Indirect Register
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Command Register
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Mode Register
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Interrupt Enable Register
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Status Register
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Counter Toggle Register
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Synch Control Register
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Increment/In-Phase/Begin Control Register
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Decrement/Quadrature/End Control Register
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Status 0 Control Register
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Status 1 Control Register
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Status 2 Control Register
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Status 3 Control Register
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Pin 0 Control Register
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Pin 1 Control Register
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Pin 2 Control Register
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Pin 3 Control Register
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Match 0 LSB Register
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Match 0 MSB Register
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Match 1 LSB Register
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Match 1 MSB Register
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Match 2 LSB Register
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Match 2 MSB Register
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Match 3 LSB Register
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Match 3 MSB Register
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Count Limit LSB Register
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Count Limit MSB Register
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Count Begin LSB Register
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Count Begin MSB Register
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Count End LSB Register
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Count End MSB Register
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Count Value LSB Register
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Count Value MSB Register
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3.3 Block Control
Each I/O block is controlled through a set of registers, listed in Section 3.2. Only the Pointer Register and the Indirect Register are accessible directly from the external interface. All the other registers within the I/O block are accessed by first writing the register address to the Pointer Register and then reading from or writing to the Indirect Register. Reading from or writing to the Indirect Register can increment the Pointer Register automatically to address the next sequential register in the I/O block if bit 7 of the Pointer Register is set.. This feature can reduce the number of address writes required when accessing multi-byte values.
3.4 Register Descriptions
3.4.1 Pointer and Indirect Registers
Each I/O block can only be accessed through the block's Pointer Register and Indirect Register. The Pointer Registers specify the addresses of the internal registers, and the Indirect Registers access the data for that internal register. When the most significant bit of the Pointer Register is set by writing the internal register address, the Pointer Register will increment automatically after each read or write to the Indirect Register.
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Pointer Register x (PR0) (External Address = 0x00)
(PR1) (External Address = 0x02)
(PR2) (External Address = 0x04)
(PR3) (External Address = 0x06)
(PR4) (External Address = 0x08 )
(PR5) (External Address = 0x0A)
(PR6) (External Address = 0x0C)
(PR7) (External Address = 0x0E)
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Disable pointer auto-increment.
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Enable pointer auto-increment.
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These bits are ignored during writes and always return zero when read.
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These five bits hold the block register address for indirect access.
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Indirect Register x (IR0) (External Address = 0x01)
(IR1) (External Address = 0x03)
(IR2) (External Address = 0x05)
(IR3) (External Address = 0x07)
(IR4) (External Address = 0x09)
(IR5) (External Address = 0x0B)
(IR6) (External Address = 0x0D)
(IR7) (External Address = 0x0F)
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Data from the register addressed by the Pointer Register are returned.
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Data is written to the register addressed by the Pointer Register.
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3.4.2 Command Register
The Command Register can internally generate a signal that would otherwise come from an external source. For example, it can force a synch signal that would normally come from the GSYNC pin or from any of the I/O block's pins.
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Command Register (CR) (Pointer = 0x00)
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No operation. This bit always reads a zero.
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Reset counter to all zeros.
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No operation. This bit always reads a zero.
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Force a synch signal.
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No operation. This bit always reads a zero.
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Force an Increment/Begin signal.
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No operation. This bit always reads a zero.
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Force a Decrement/End signal.
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These bits are reserved an should not be used.
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3.4.3 Mode Register
The Mode Register defines the overall function of the I/O block by specifying how the 16-bit counter will be used.
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Mode Register (MR) (Pointer = 0x01)
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These bits are ignored and should not be used.
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Use the master clock directly (for both input synchronizers and timer).
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Use prescaler output clock (for both input synchronizers and timer).
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Disable counter/timer.
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Enable counter mode. Count forever on Increment/In-Phase/Begin signal.
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Enable counter mode. Count until any match condition on Increment/In-Phase/Begin signal.
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Enable counter mode. Count up on Increment/In-Phase/Begin and count down on Decrement/Quadrature/End.
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Enable timer mode. Counter runs continuously.
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Enable timer mode. Counter runs continuously, until the End condition.
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Enable timer mode. Counter runs from Begin condition until the End condition.
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Enable timer mode. Counter counts continuously during the Begin condition.
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3.4.4 Interrupt Enable and Status Registers
Controlling I/O block interrupts is a matter of writing to the proper bits of the Interrupt Enable Register (IER). The generation of an interrupt defined by the IER is registered to the block's Status Register (SR). The block interrupt will in turn be registered to the Master Status Register (MSR).
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Interrupt Enable Register (IER) (Pointer = 0x02)
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Disable Decrement/Quadrature/End interrupt.
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Enable Decrement/Quadrature/End interrupt
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Disable Increment/In-Phase/Begin interrupt.
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Enable Increment/In-Phase/Begin interrupt.
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Disable counter rollover (decrement) interrupt.
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Enable counter rollover (decrement) interrupt.
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Disable counter rollover (increment) interrupt.
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Enable counter rollover (increment) interrupt.
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Disable Match 3 interrupt.
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Enable Match 3 interrupt.
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Disable Match 2 interrupt.
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Enable Match 2 interrupt.
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Disable Match 1 interrupt.
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Enable Match 1 interrupt.
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Disable Match 0 interrupt.
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Enable Match 0 interrupt.
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Status Register (SR) (Pointer = 0x03)
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No operation
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Clear the corresponding interrupt condition
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No Decrement/Quadrature/End interrupt condition pending.
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Decrement/Quadrature/End interrupt condition pending.
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No Increment/In-Phase/Begin interrupt condition pending
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Increment/In-Phase/Begin interrupt condition pending.
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No counter rollover (increment) interrupt condition pending.
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Counter rollover (increment) interrupt condition pending.
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No Counter Rollover (decrement) interrupt condition pending.
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Counter Rollover (decrement) interrupt condition pending.
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No Match 3 interrupt condition pending.
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Match 3 interrupt condition pending.
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No Match 2 interrupt condition pending.
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Match 2 interrupt condition pending.
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No Match 1 interrupt condition pending.
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Match 1 interrupt condition pending.
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No Match 0 interrupt condition pending.
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Match 0 interrupt condition pending.
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3.4.5 Counter Toggle Register
The toggle function imposes a fixed frequency/duty cycle "mask" over the output when it would otherwise be continuously high. The duty cycle may be set to 50%, 25%, 12.5%, and so on by writing to this register. The purpose of this function is generally to reduce driver current for applications such as relay coils or thyristor gate drivers that control loads.
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Counter Toggle Register (CTR) (Pointer = 0x04)
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Deselect the corresponding bit of the counter as the toggle signal.
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Select the corresponding bit of the counter as the toggle signal. Select one bit for a 50% duty cycle. Select two adjacent bits for a 25% duty cycle, and so on. The actual toggle signal is generated as Toggle = &(~CTR | Counter[7:0]).
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The output will toggle whenever the pin is supposed to output a logic one.
The diagram below shows how Counter [0] and Counter [1] would look relative to each other, and then shows the effects of toggling an output with Counter [0].
3.4.6 Synch Control Register
The Synch Control Register is used to select the pin that will be used as the synch signal for that particular I/O block. A pin used as a synch signal can reset the block's counter. Similarly, the GSYNC signal has the ability to reset all the I/O blocks on the Rabbit RIO if it is selected to do so.
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Synch Control Register (SCR) (Pointer = 0x05)
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Synch signal does not affect counter.
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Enable synch signal to reset counter.
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This bit is reserved and should not be used.
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Disable synch signal, without generating an edge.
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Synch signalled on rising edge.
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Synch signalled on falling edge.
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Synch signalled on either edge.
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This bit combination is reserved and should not be used.
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This bit combination is reserved and should not be used.
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Synch signalled while low.
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Synch signalled while high.
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No selection. Selector output is low.
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This bit combination is reserved and should not be used.
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This bit combination is reserved and should not be used.
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Select Global Synch.
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Select Pin[0].
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Select Pin[1].
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Select Pin[2].
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Select Pin[3].
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3.4.7 Increment/In-Phase/Begin Control Register
This register controls which pin is used to increment the counter, act as the in-phase input to a quadrature decoder, or begin the counter. It also controls how that pin is detected, whether it be by an edge, by a level, or by a transition.
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Increment/In-Phase/Begin Control Register (ICR) (Pointer = 0x06)
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These bits are reserved and should not be used.
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Disable Increment/In-Phase/Begin signal without generating an edge
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Increment/In-Phase/Begin signal on rising edge.
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Increment/In-Phase/Begin signal on falling edge.
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Increment/In-Phase/Begin signal on either edge.
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Increment/In-Phase/Begin signal on 10 ® 11 ® 01 ® 00 ® 10 quadrature decoder transitions.
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This bit combination is reserved and should not be used.
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Increment/In-Phase/Begin signal while low.
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Increment/In-Phase/Begin signal while high.
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No selection. Selector output is low.
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This bit combination is reserved and should not be used.
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This bit combination is reserved and should not be used.
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Select Global Synch.
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Select Pin[0].
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Select Pin[1].
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Select Pin[2].
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Select Pin[3].
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3.4.8 Decrement/Quadrature/End Control Register
Similar to the Increment/In-Phase/Begin Control Register (ICR), the Decrement/Quadrature/End Control Register (DCR) complements the ICR in its function to decrement the counter, act as the quadrature input to a quadrature signal, or stop the counter. It also controls how that pin is detected, whether it be by an edge, level, or transition.
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Decrement/Quadrature/End Control Register (DCR) (Address = 0x07)
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These bits are reserved and should not be used.
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Disable Decrement/Quadrature/End signal without generating an edge
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Decrement/Quadrature/End signalled on rising edge.
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Decrement/Quadrature/End signalled on falling edge.
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Decrement/Quadrature/End signalled on either edge.
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Decrement/Quadrature/End signalled on 01 ® 11 ® 10 ® 00 ® 01 quadrature decoder transitions.
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This bit combination is reserved and should not be used.
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Decrement/Quadrature/End signalled while low.
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Decrement/Quadrature/End signalled while high.
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No selection. Selector output is low.
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This bit combination is reserved and should not be used.
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This bit combination is reserved and should not be used.
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Select Global Synch.
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Select Pin[0].
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Select Pin[1].
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Select Pin[2].
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Select Pin[3].
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3.4.9 Status Control Registers
The Status Control Registers determine how the status signal is generated, if at all.
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Status x Control Register (S0CR) (Address = 0x08)
(S1CR) (Address = 0x09)
(S2CR) (Address = 0x0A)
(S3CR) (Address =0x0B)
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These bits are reserved and should not be used.
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Status x not set by internal conditions.
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Status x set by counter rollover (decrement).
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Status x set by counter rollover (increment).
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Status x set by synch signal.
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Status x set by Match 0 condition.
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Status x set by Match 1 condition.
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Status x set by Match 2 condition.
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Status x set by Match 3 condition.
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Status x reset by internal conditions.
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Status x reset by counter rollover (decrement).
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Status x reset by counter rollover (increment).
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Status x reset by synch signal.
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Status x reset by Match 0 condition.
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Status x reset by Match 1 condition.
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Status x reset by Match 2 condition.
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Status x reset by Match 3 condition.
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3.4.10 Pin Control Registers
The Pin Control Registers determine the overall function of a pin.
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Pin x Control Register (P0CR) (Address = 0x0C)
(P1CR) (Address = 0x0D)
(P2CR) (Address = 0x0E)
(P3CR) (Address = 0x0F)
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These bits return the current state of Pin[3:0].
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These bits store the output data for Pin[3:0] (P3CR only).
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This bit is reserved and should not be used.
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Pin bit is an input.
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This bit combination is reserved and should not be used.
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This bit is an output — Status x & Toggle.
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Pin bit is an output — Status x
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Pin bit is an output: use appropriate bit of PxCR. Sequence through P0CR-P1CR-P2CR-P3CR, changing on each counter (increment) rollover.
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Pin bit is an output: use appropriate bit of P3CR.
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Pin bit is an output — low.
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Pin bit is an output — high.
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3.4.11 Match Registers
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Match x LSB Register (M0LR) (Address = 0x10)
(M1LR) (Address = 0x12)
(M2LR) (Address = 0x14)
(M3LR) (Address = 0x16)
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Match x MSB Register (M0MR) (Address = 0x11)
(M1MR) (Address = 0x13)
(M2MR) (Address = 0x15)
(M3MR) (Address = 0x17)
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When the current count equals the value held in this register, the Match x signal is true. This signal can be used to set a status signal and generate an interrupt request. The value in this register is loaded into a holding register for the comparison each time the counter is reloaded to allow modification of the match value during the current count cycle.
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3.4.12 Count Limit Registers
The Count Limit Register is a 16-bit register used to tell the counter that the end of the counting cycle has been reached and to reset.
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Count Limit LSB Register (CLLR) (Address = 0x18)
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Count Limit MSB Register (CLMR) (Address = 0x19)
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When the counter reaches the value held in one of these registers (plus 1), the counter will be reset to all zeros, effectively causing division by n + 1. For example, this means placing an 8 in the register means a divide by 9.
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3.4.13 Count Begin Registers
At the trigger of the Begin signal, the value of the counter is latched into the Count Begin Registers.
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Count Begin LSB Register (CBLR) (Address=0x1A)
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Count Begin MSB Register (CBMR) (Address=0x1B)
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These registers return the count that was latched by the Begin condition. The value that is ready is guaranteed to be stable by freeing the read data while the pointer is pointing to either of these registers. This latching function is independent of the latches controlled by the Begin condition.
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3.4.14 Count End Registers
At the trigger of the End signal, the value of the counter is latched to the Count End Registers.
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Count End LSB Register (CELR) (Address=0x1C)
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Count End MSB Register (CEMR) (Address=0x1D)
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These registers hold the count that was latched by the End condition. The value that is read is guaranteed to be stable by freezing the read data while the pointer is pointing to either of these registers. This latching functions is independent of the latches controlled by the End condition.
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3.4.15 Count Value Registers
At any point during the count cycle, the value of the counter can be read from this register.
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Count Value LSB Register (CVLR) (Address = 0x1E)
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Count Value MSB Register (CVMR) (Address=0x1F)
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The current count is returned. The value that is read is guaranteed to be stable by freezing the read data while the pointer is pointing to either of these registers. This implies that the pointer must be modified to point at another register to allow a new current count to be read.
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