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Appendix B. I/O Register and Interrupt Vector Access

This chapter discusses the I/O register set of the Rabbit processor, as well as the interrupt vectors an application can use.

Each register has an associated access level in the range 1 through 3. Registers at level 1 or 2 may be accessible to an application; it depends on the the protection mode of RabbitSys. Level 1 and 2 registers are always available in unprotected mode; their availability in protected mode is listed in Section B.3. (

Level 3 registers are never accessible to an application1. (See Section B.2 for a list of level 3 registers).

B.1 User Enable Registers and the Registers they Control

User enable registers are never accessible to an application (see Section B.2); however, they do control access to other I/O registers that may be accessible to an application. Table 1 lists the user enable register mnemonics and the corresponding registers at levels 1 and 2 which they control.

Table B-1. I/O Registers at Level 1 and 2 Enabled by User Enable Registers

User Enable Register

Address Range Enabled

I/O Registers in Address Range 


RTUER


0x02 - 0x07

Real-time clock: RTCxR 


VBUER


0x600 - 0x61F

Battery-Backed RAM: VRAM00 - VRAM1F 


SPUER


0x20 - 0x27

Slave port: SPCR, SPDxR, SPSR 


PAUER


0x30 - 0x37

Parallel port A: PADR 


PBUER


0x40 - 0x47

Parallel port B: PBDR, PBDDR 


PCUER


0x50 - 0x55

Parallel port C: PCDR, PCFR 


PDUER


0x60 - 0x6F

Parallel port D: PDDR, PDCR, PDBxR, PDDCR, PDDDR, PDFR 


PEUER


0x70 - 0x7F

Parallel port E: PEDR, PECR, PEBxR, PEDDR, PEFR 


PFUER 


0x38 - 0x3F

Parallel port F: PFDR, PFCR, PFDCR, PFDDR, PFFR (Rabbit 3000A only) 


PGUER


0x438 - 0x4F

Parallel port G: PGDR, PGCR, PGDCR, PGDDR, PGFR (Rabbit 3000A only) 


ICUER


0x56 - 0x5F

Input capture: ICCR, ICCSR, ICLxR, ICMxR, ICSxR, ICTxR 


IBUER


0x80 - 0x87

I/O bank control: IBxCR 


PWUER


0x88 - 0x8F

Pulse width modulation: PWLxR, PWMxR, 


QDUER


0x90 - 0x97

Quadrature Decoder: QDCR, QDCSR, QDCxR, QDCxHR 


IUER


0x98 - 0x9F

External interrupt: IxCR 


TAUER


0xA0 - 0xAF

Timer A: TACR, TACSR, TAPR, TATxR 


TBUER


0xB0 - 0xBF

Timer B: TBCLR, TBCMR, TBCR, TBCSR, TBLxR, TBMxR 


TCUER


0x500 - 0x50F

Timer C: TCCSR, TCCR, TCDLR, TCDHR, TCS0LR, TCS0HR, TCR0LR, TCR0HR, TCS1LR, TCS1HR, TCR1LR, TCR1HR, TCBAR, TCBPR 


SAUER


0xC0 - 0xC7

Serial port A: SAAR, SACR, SADR, SAER, SALR, SASR 


SBUER


0xD0 - 0xD7

Serial port B: SBAR, SBCR, SBDR, SBER, SBLR SBSR 


SCUER


0xE0 - 0xE7

Serial port C: SCAR, SCCR, SCDR, SCER, SCLR SCSR 


SDUER


0xF0 - 0xF7

Serial port D: SDAR, SDCR, SDDR, SDER, SDLR SDSR 


SEUER


0xC8 - 0xCF

Serial port E: SEAR, SECR, SEDR, SEER, SELR SESR 


SFUER


0xD8 - 0xDF

Serial port F: SFAR, SFCR, SFDR, SFER, SFLR, SFSR


B.2 Registers Unavailable in User Mode

A number of internal registers are never accessible by code running in User mode because they can affect the global operation of the device. These registers are listed below.

Table B-2. I/O Registers at Level 3

Register Mnemonic

Register Name 


BDCR

Breakpoint/Debug Control Register 


BxCR

Breakpoint x Control Register 


DATASEG

Data Segment Register 


DATSEGL

Data Segment Low Register 


DATSEGH

Data Segment High Register 


EDMR

Enable Dual Mode Register 


GCDR

Global Clock Double Register 


GCSR

Global Control/Status Register 


GCM0R

Global Clock Modulator 0 Register 


GCM1R

Global Clock Modulator 1 Register 


GPSCR

Global Power Save Control Register 


GOCR

Global Output Control Register 


MACR

Memory Alternate Control Register 


MBxCR

Memory Bank x Control Register 


MECR

MMU Expanded Code Register 


MMIDR

MMU Instruction/Data Register 


MTCR

Memory Timing Control Register 


RAMSR

RAM Segment Register 


RTCCR

Real-Time Clock Control Register 


SEGSIZ

Segment Size Register 


STKSEG

Stack Segment Register 


STKSEGL

Stack Segment Low Register 


STKSEGH

Stack Segment High Register 


SWDTR

Secondary Watchdog Timer Register 


WDTCR

Watchdog Timer Control Register 


WDTTR

Watchdog Timer Test Register 


IUER, IBUER, ICUER, PAUER,
PBUER, PCUER, PDUER, PEUER,
PFUER, PGUER, QDUER, RTUER,
SAUER, SBUER, SCUER, SDUER,
SEUER, SFUER, SPUER, TAUER,
TBUER, TCUER

User Enable Registers 


STKCR, STKLLR, STKHLR, WPCR,
WPLR, WPHR, WPxR, WPSAR, WPSBR,
WPSALR, WPSBLR, WPSAHR, WPSBHR

Memory Protection Registers


B.3 Register Permissions

In this section are the register permissions for the RCM3365. For each bit position, a "0" means that RabbitSys uses that bit and it is not available to an application when running in protected mode. A "1" means that the bit is available to an application when running in protected mode.

Table B-3. Register Bit Permissions for the RCM3365
Running in RabbitSys Protected Mode

Register Mnemonic

Bit Permissions [7,0] 


RTCCR, RTCxR
1111 1111
 

GOCR1
1100 1011
 

SPSR, SPDxR
1111 1111
 

SPCR
0000 0000
 

GROM, GRAM
1111 1111
 

GCPU, GREV
1111 1111
 

PADR
1111 1111
 

PBDR, PBDDR
1111 1111
 

PCDR, PCFR
1111 1111
 

PDDR, PDCR, PDFR, PDDCR, PDDDR, PDBxR
1111 1111
 

PEDR, PEFR, PEDDR
1111 1010
 

PECR
1111 0000
 

PEB0R, PEB1R, PEB3R, PEB4R, PEB5R, PEB6R, PEB7R
1111 1111
 

PEB2R
0000 0000
 

PFDR, PFCR, PFFR, PFDCR, PFDDR
1111 1111
 

PGDR, PGCR, PGFR, PGDCR, PGDDR
1111 1111
 

ICCSR, ICCR, ICTxR, ICSxR, ICLxR, ICMxR
1111 1111
 

IB0CR, IB1CR, IB3CR, IB4CR, IB5CR, IB6CR, IB7CR
1111 1111
 

IB2CR
0000 0000
 

PWLxR, PWMxR
1111 1111
 

QDCSR, QDCR, QDC1R, QDC2R
1111 1111
 

I0CR, I1CR
1111 1111
 

TACSR, TAPR, TACR, TATxR
1111 1111
 

TBCSR, TBCR, TBMxR, TBLxR, TBCMR, TBCLR
1111 1111
 

SADR, SAAR, SALR, SASR, SACR, SAER
1111 1111
 

SBDR, SBAR, SBLR, SBSR, SBCR, SBER
1111 1111
 

SCDR, SCAR, SCLR, SCSR, SCCR, SCER
1111 1111
 

SDDR, SDAR, SDLR, SDSR, SDCR, SDER
1111 1111
 

SEDR, SEAR, SELR, SESR, SECR, SEER
1111 1111
 

SFDR, SFAR, SFLR, SFSR, SFCR, SFER
1111 1111

1 This register is available to an application that is executing a syscallable function. See Section 3.4 for more details.

B.4 Interrupt Vectors

The following interrupt vectors are available to an application running on an RCM3365-based system in both protected and unprotected mode.

External Interrupt 0

RST10

Serial Port E

External Interrupt 1

RST38

Serial Port F

Input Capture

Serial Port B

Slave Port

PWM

Serial Port C

Timer A

Quadrature Decoder

Serial Port D

Timer B


1 There are some exceptions regarding level 3 registers if the application is executing a user-defined syscallable function. The exceptions are noted in the tables in Section B.3 that describe register bit permissions.
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